Gentlemen, start your drooling

[unixronin]

IBM is taking the wraps off the Power7 architecture.

Eight cores per chip with four-way simultaneous multithreading on each core.  That's 32 simultaneous threads executing on one CPU.  Dual DDR3 memory controllers for 100GB/sec of sustained memory bandwidth per chip.  32MB of shared L3 eDRAM cache in the center of each chip is almost as fast as SRAM, but takes a third of the space and consumes a fifth of the standby power, and IBM claims six times better latency than off-chip L3 cache.  Imagine having your entire OS kernel in cache.  Power saving options include a CPU sleep mode that drops voltage to the minimum required to maintain state, and data-integrity features include 64-byte ECC, the ability to do RAM mirroring, and CPU fail-over.

And they've already ported Linux to it, both natively and in x86 emulation mode, as well as AIX and IBM's i OS.

Gentlemen, start your drooling.  There's a new big dog on the block.

Comments

[randwolf.livejournal.com]

Now, what will the systems built around this technology look like?

[wyrdling.livejournal.com]

hey us ladies can do some mighty drooling, too! ;)

[zaitcev.livejournal.com]

It's pretty interesting, but the clock rate is suspiciously missing.